Appeal No. 2002-2195
Application No. 08/988,616
Appellants assert, in response to the section 102 rejection over Sawase, that the
reference fails to teach “invoking an instruction fetch to retrieve data from a
predetermined address in the microcode ROM,” as set forth in instant claim 60.
According to appellants, Sawase does not disclose or suggest any method or apparatus
that uses an instruction fetch mechanism to read data from a predetermined location in
the EEPROM. Appellants allege, further, that it is not possible for the EEPROM test
circuit as disclosed in Sawase to invoke any instruction fetch from the CPU because
only the EEPROM module is operative during the testing, and isolated from the CPU,
RAM, and ROM. (Brief at 11.)
The examiner responds that instant claim 60 does not require that the instruction
fetch invocation be from a CPU. The examiner finds that the claimed “invoking an
instruction fetch” is taught by the data read-out occurring in response to control signals
provided from outside the semiconductor circuit, pointing to column 3, lines 28 through
31 of the reference. (Answer at 5.)
Instant claim 60 does not specify the mechanism that invokes the instruction
fetch, nor the location of the mechanism. We are not persuaded of error in the
examiner’s position. In particular, appellants have not shown why the read operation
described in column 3 of Sawase, although retrieving data from a predetermined
address in the EEPROM, must be considered different from the claimed step of
invoking an instruction fetch to retrieve the data.
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