Appeal No. 2002-2195
Application No. 08/988,616
We also consider appellants’ arguments at pages 12 through 15 of the Brief as
failing to show error in the examiner’s position with respect to the second step of instant
claim 60. There appears to be no dispute that the reference teaches that EEPROM
module 9 (Fig. 2) is isolated from the CPU, RAM, and ROM during testing. See
Sawase col. 3, ll. 9-12. Instant claim 60 does not specify how, or by what means,
execution of the data is suppressed, other than that the suppressing is “in response to a
signal indicating a test mode.” As described at column 3 of Sawase, when the test
control signals are applied to test circuit 8 (Fig. 1), data from EEPROM matrix 10 is read
out by an external structure via test I/O data buffer 18 (Fig. 2). The retrieved data is not
executed by CPU 2, which is isolated from the EEPROM during test mode. Nor, for that
matter, is the retrieved data executed by the external test instruments, since during test
mode the EEPROM is checked for integrity of stored data, rather than serving as a
source for executable instructions. In short, the data retrieved during the test mode is
not executed in any case. We agree with the examiner that Sawase teaches not
executing, and thus fairly teaches suppressing execution, of the retrieved data.
Instant claim 67 is narrower than claim 60 in requiring that “the microprocessor
suppresses execution of the data retrieved.” Appellants’ arguments (Brief at 17-18)
appear to equate CPU 2 of Sawase (Fig. 1) with a “microprocessor” within the meaning
of the claim. However, consistent with the preamble of claim 67 and with the disclosure
of Sawase, the “microprocessor” consists of more than a CPU. All the circuitry shown
on substrate 1 in Sawase, including that which ensures that EEPROM module 9 is
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