Appeal No. 2003-0902
Application No. 09/332,413
instruction group (specification, page 5, lines 20-33).
Following the fetching of multiple instructions, the fetched
instructions are divided into and dispatched as groups, with each
group having a first or last instruction that is an interruptible
instruction (Figures 3, 7, and 9).
Claims 3 and 5 are representative of the claimed invention
and are reproduced as follows:
3. A method of increasing the efficiency of execution of a
processor, comprising:
dispatching instructions in instruction groups, wherein if
an instruction group contains an interruptible instruction of a
selected type, only one interruptible instruction of said
selected type is included in said instruction group, wherein said
interruptible instruction of said selected type is dispatched at
the front of said instruction group;
recording a state for the processor associated with a
dispatched instruction group; and
restoring said processor to said recorded state associated
with said dispatched instruction group containing said
interruptible instruction of said selected type causing an
interrupt, in response to said interrupt from one of said
interruptible instructions of said selected type.
5. A method of increasing the efficiency of execution of a
processor comprising:
searching a group of N fetched instructions for an
interruptible instruction of said selected type;
dispatching said group of N fetched instructions in response
to not finding said interruptible instruction of said selected
type in said group of N fetched instructions;
2
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