Appeal No.2003-1091
Application No. 09/484,248
clock signal line, coupled to a clock input on each multiplexer,
which provides synchronous phase aligned clock signals to each
clock input from a clock signal source. In response to changes
in the control signal, associated delay elements are removed or
added to the delay line in single step.
Claim 1 is illustrative of the invention and reads as
follows:
1. A digital delay line, comprising:
(a) a plurality of multiplexer delay elements arranged in
sequence each of said plurality of multiplexer delay
elements having an associated control input;
(b) a clock signal line coupled to a clock input of each of
said plurality of multiplexers, said clock signal line
operative to provide synchronous phase aligned clock
signals from a clock signal source to each of said
clock inputs; and
(c) a control input coupled to each of said plurality of
multiplexer delay elements operative to transmit to
each of said plurality of multiplexer delay elements an
associated control signal and, in response to said
control signal, to select or deselect, in a single
step, up to a plurality of delay elements from a start
of said delay line.
The Examiner relies on the following prior art references:1
Butcher 4,789,996 Dec. 06, 1988
Takano et al. (Takano) 5,940,414 Aug. 17, 1999
Claims 1 and 14 stand finally rejected under 35 U.S.C.
§ 102(b) as being anticipated by Butcher. Claims 2-13 and 15-20
1 In addition, the Examiner relies on Appellant’s admissions as to a
prior art clocking structure illustrated at Figure 1 in Appellant’s drawings.
2
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