Appeal No. 2003-1218
Application No. 09/019,278
BACKGROUND
The invention relates to a family of logic for implementation in semiconductor
devices. According to appellants, implementation of the logic provides advantages over
traditional CMOS logic circuitry. Representative Claim 1 is reproduced below.
1. A 1 of N signal used to convey multiple values of information between
N-NARY logic circuits in an integrated circuit, comprising:
a bundle of N wires routed together between different N-NARY logic
circuits in the integrated circuit wherein at most one wire of said bundle of N
wires is active during an evaluation cycle and where N is greater than 2; and
a 1 of N encoding that encodes said bundle of N wires to indicate multiple
values of information conveyed by said bundle of N wires wherein at most one
wire of said bundle of N wires is true during said evaluation cycle.
The examiner relies on the following reference:
Remedi 4,176,287 Nov. 27, 1979
Claims 1-16 stand rejected under 35 U.S.C. § 102 as being anticipated by
Remedi.
We refer to the Final Rejection (Paper No. 23) and the Examiner’s Answer
(Paper No. 26) for a statement of the examiner’s position and to the Brief (Paper No.
25) and the Reply Brief (Paper No. 27) for appellants’ position with respect to the claims
which stand rejected.
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