Appeal No. 2003-1218
Application No. 09/019,278
OPINION
Remedi describes CMOS decoders, such as a 1 of 16 decoder depicted in Figure
1. The decoder of Figure 1 contains digital inputs A0 through A3, and 16 output lines, 0
to 15. Col. 2, ll. 15-26.
The rejection reads the claimed “bundle of N wires” on outputs 0 through 15, and
the “1 of N encoding” on element 20, which is the entire CMOS decoder of Remedi’s
Figure 1. (Answer at 3-4.) However, the reference circuit is a 1 of 16 decoder. Remedi
does not describe any form of 1 of 16 “encoding.”
In any event, the rejection also asserts that “at most one wire of the 1 of N
encoded the bundle of N wires [sic] is true during the evaluation.” (Answer at 4.)
Remedi describes one of sixteen possible outputs that are selected depending on the
states of inputs A0 through A3 (e.g., col. 4, ll. 21-31). One of the sixteen outputs may
fairly be regarded as “true” upon completion of the decoding of the inputs. However,
Remedi does not appear to discuss an “evaluation cycle,” much less “at most one wire”
being true during the evaluation cycle, as claimed. Further, we disagree with the
implied premise, at page 5 of the Answer, that the claims require no more than “a
bundle of wires carrying a known signal format ‘1 of N signal.’”
“Anticipation is established only when a single prior art reference discloses,
expressly or under principles of inherency, each and every element of a claimed
invention.” RCA Corp. v. Applied Digital Data Sys., Inc., 730 F.2d 1440, 1444, 221
USPQ 385, 388 (Fed. Cir. 1984). Since Remedi does not expressly describe subject
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