Appeal No. 2003-1240
Application No. 09/304,964
statement of the rejection and the remainder of the responsive arguments, the
“memory” appears to be exemplified by FIFO 110, shown in Figure 7 of Wu.
Wu’s FIFO’s 110, 120, and 140 are contained within cell input unit (CIU) 100.
Col. 13, l. 47 et seq. Processor 200 (Fig. 8) comprises a number of such CIU’s. Col.
15, l. 55 et seq.
Instant claim 2 recites that the scheduler is configured to receive a request for a
time slot from a queuing device (e.g., a FIFO) when the queuing device holds data to be
processed by the logic circuitry. Processor 200 of Wu contains priority circuit 260,
which sequences the outputting of cells from each of the output FIFO’s 230, 240, and
250. Col. 16, ll. 26-65. Instant claim 2 also requires, however, that the plurality of
queuing devices correspond to the plurality of receive ports, which might suggest
(multiple instances of) FIFO 110, which receive (or receives) the cells from a cell source
(e.g., col. 13, ll. 58-62).
However, Wu describes, in express terms, the scheduling of cells. Column 16,
lines 26 through 65 describe how cells in output FIFO’s 230, 240, and 250 are
sequenced for output. Column 13, line 47 through column 15, line 54 describes how
token generator circuits 160 and 170 transmit tokens to switches 130 and 150, and
further describes the use of clock signals, to assign priority states to the cells produced
by the particular source. The rejection does not explain how Wu’s detailed disclosure
of cell scheduling might meet the terms of instant claim 2, but relies on inherency -- i.e.,
what “must” be true of Wu’s system.
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