Appeal No. 2003-1367
Application No. 09/640,237
patterning a first deposition material on said first barrier layer and said at least one transistor
gate member, wherein said first deposition material includes individual openings over
each of said at least one drain contact plugs and each of said at least one source
contact plugs;
depositing a layer of second conductive material over said first deposition material to fill said
individual openings over each of said at least one drain contact plugs and each of said
at least one source contact plugs;
planarizing said second conductive material to said first deposition material to form an
individual drain contact land over each of said at least one drain contact plugs and an
individual source contact land over each of said at least one source contact plug;
removing said first deposition material;
depositing a second barrier layer over said first barrier layer and said individual drain contact
lands and said individual source contact lands;
patterning a second etch mask on said second barrier layer, wherein said second etch mask
includes openings substantially over said individual drain contact lands and over said
individual source contact lands;
etching said second barrier layer to expose said at least one drain contact land and said at
least one source contact land forming at least one drain contact via and at least one
source contact via, respectively;
removing said second etch mask;
depositing a layer of third conductive material over said etched second barrier layer to fill
said at least one drain contact via and said at least one source contact via; and
planarizing said third conductive material forming at least one upper drain contact and at
least one upper source contact in said at least one drain contact via and said at least
one source contact via, respectively.
The appealed claim 1 is directed to a method of making a contact for a semiconductor
device having a contact land covering only a single contact plug. The contact landing pads
render the fabrication of semiconductor devices "less sensitive to alignment constraint in the
formation of contacts." (Spec., page 6.) The appealed claim 8 is directed to a method of making
a bipolar transistor for the dissipation of electrostatic discharges that includes the steps, among
others, of forming an individual source contact land and "planarizing said first barrier layer to
expose said at least one transistor gate member."
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