Appeal No. 2003-1367
Application No. 09/640,237
conclusive by this court."). Instead, appellant argues that, even assuming that this statement is
true, a prima facie case has not been set forth. Specifically, appellant argues that "Nguyen et al.
specifically teaches that a flat dielectric layer 40 is undesirable." (Appeal Brief, page 8.) We
disagree. Appellant has not pointed out where Nguyen "specifically" teaches that a flat dielectric
layer 40 would have been undesirable. Appellant's contention that Nguyen teaches away from
"planarizing" appears to be based solely on the figures, which depict a non-planar layer 40, and
the bare fact that Nguyen does not teach global planarization. This is not the kind of teaching
that would "teach away" in the sense of defeating obviousness since there is nothing that
suggests that planarizing any portion of Nguyen would likely be unproductive of the claimed
result. See In re Gurley, 27 F.3d 551, 552, 31 USPQ2d 1130, 1132 (Fed. Cir. 1994) ("[A]
reference will teach away if it suggests that the line of development flowing from the reference's
disclosure is unlikely to be productive of the result sought by the applicant."). We find that
nothing in Nguyen suggests that it is undesirable to planarize a portion of the dielectric layer 40
above the transistor gate.
Appellant further contends that applying Nakamura's teaching of reflow "would result in
an absence of dielectric layer 40 covering the transistor structure 12 and 20 and may endanger
the integrity of the transistor structures 12 and 20." (Appeal Brief, page 8.) Indeed, appellant
goes so far as to state that "any planarization, or polishing, of the dielectric layer 40 of Nguyen et
al. would necessarily result in the planarization of the covered structure down to the dielectric
layer 40 surface." (Appeal Brief, page 9.) Both of the foregoing arguments result from
appellant's incorrect understanding of the breadth of the term "planarizing." It suffices to say
that the term "planarizing" as claimed does not require global planarization and thus one would
not need to create an "absence of dielectric layer 40 covering the transistor structure 12 and 20"
or "planarization of the covered structure down to the dielectric layer" before fully meeting the
claimed "planarizing" limitation. Accordingly, we find no error in the combination of Nguyen
with Nakamura under 35 U.S.C. § 103(a).
We now consider the grounds of rejection of claims 3 and 4 under 35 U.S.C. § 103(a)
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