Ex Parte YOSHIDA et al - Page 2




              Appeal No. 2003-1622                                                                                        
              Application No. 09/146,529                                                                                  


                     Appellants’ invention relates to a data processing device.  An understanding of                      
              the invention can be derived from a reading of exemplary claim 1, which is reproduced                       
              below.                                                                                                      
                     1.     A data processing device comprising:                                                          
                            an instruction decoder for sequentially decoding a plurality of                               
                     instructions described in a program sequence and outputting control                                  
                     signals respectively corresponding to the instructions, and                                          
                            an instruction execution unit for executing operations respectively                           
                     designated by said plurality of instructions in accordance with said control                         
                     signal output from said instruction decoder, wherein                                                 
                            said instruction decoder decodes a first instruction among said                               
                     plurality of instructions and outputs a first control signal in a first period;                      
                            said instruction execution unit executes the operation designated by                          
                     said first instruction in accordance with said first control signal in a second                      
                     period succeeding to said first period;                                                              
                            said instruction decoder outputs a second control signal in a third                           
                     period by decoding a second instruction of which operation is executed                               
                     under a predetermined condition among said plurality of instructions; and                            
                            said instruction execution unit determines whether or not said                                
                     predetermined condition is satisfied in a fourth period and executes the                             
                     operation designated by said second instruction in response to a result of                           
                     the determination, said fourth period being started after elapsing a same                            
                     time as said second period or longer from an ending of said third period.                            

                     The prior art of record relied upon by the examiner in rejecting the appealed                        
              claims is as follows:                                                                                       
              Holmann et al. (Holmann)                   JP 08203675                  Feb. 20, 1998                       

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