Appeal No. 2003-2038
Application 09/288,833
parallel video compression circuits 120 and 130. Adams clearly
intends that the two decompression circuits 120 and 130 comprise
buffers that are identical to one another. Appellants argue that
Adams does not teach or remotely suggest that the buffers are of
unequal size or that they have different buffering delays
associated therewith as required by Appellants’ claims. See
Appellants’ Reply Brief, pages 3 and 4.
We note that the Examiner has not been able to point to
the specific teaching in either Adams or Cellario that teaches
buffering data packets from one of the sequences in a first
receive buffer having a first buffering delay and buffering data
packets from another one of the sequences in a second receive
buffer having a second buffering delay, the second buffering
delay being smaller than the first buffering delay as required by
Appellants’ claims. Furthermore, we note that Adams teaches that
the buffers comprise eight 256K words by 16 bit dynamic random
access memories coupled to the decoder. See Adams, column 5,
lines 3-6. Therefore, Adams teaches that the buffers are
identical and therefore would have the same buffering delays, not
different as required by the claims.
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