Appeal No. 2003-2108
Application No. 08/881,123
Claim 1 is illustrative of the claimed invention, and it
reads as follows:
1. An apparatus having a memory controller for
controlling access to a memory by a plurality of devices,
the apparatus comprising:
a priority order controller
to generate either
an acknowledgment signal to a
corresponding one of the plurality of devices in response to
a request signal generated by the corresponding device, or
the acknowledgment signal to the
corresponding device according to a predetermined priority
order if more than one request signal is simultaneously
generated from the plurality of devices, and
to subsequently deactivate the generated
acknowledgment signal if an access actuation signal is
deactivated,
wherein the access actuation signal is distinct from
the request signal and is issued by the memory controller to
indicate that one of the plurality of devices is accessing
the memory.
The reference relied on by the examiner is:
Craft et al. (Craft) 5,438,666 Aug. 1, 1995
Claims 1, 2 and 5 through 20 stand rejected under 35 U.S.C.
§ 102(b) as being anticipated by Craft.
Reference is made to the briefs (paper numbers 31 and 34)
and the answer (paper number 32) for the respective positions of
the appellant and the examiner.
2
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