Appeal No. 2004-0393
Application 09/388,824
claim 53 is different than the product in Jimenez, except in the
way the conductive lines are intended to be used.
The examiner has unnecessarily made the rejection more
difficult by relying on 35 U.S.C. § 102 instead of § 103.
Jimenez discloses that the invention relates to fabrication of
so-called "Smart Power" components that include power elements
and a control logic portion on the same chip (col. 1,
lines 7-11). Thus, Jimenez does not teach that the control logic
portions are used for "digit lines." Jimenez discloses different
thickness metallizations for power and logic circuits used
together (col. 1, lines 13-26). In view of this teaching, it
would have been obvious to one of ordinary skill to apply Jimenez
to a memory device having both power and logic memory portions on
the same chip, where the logic memory portion necessarily
includes digit lines. The examiner's finding of "formation of
digit lines to be inherent in the disclosure of Jimenez" (answer,
p. 5) is erroneous because Jimenez does not disclose that the
logic portion of the "Smart Power" component necessarily has a
memory. The examiner's reference to Segawa in support of the
inherency rejection is not appropriate for an anticipation
rejection and, in any case, Segawa does not tend to prove that
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