Appeal No. 2004-0442
Application No. 09/222,953
Appellant's invention relates to an averaging measurement
circuit using a subtracter, an adder, and a single register.
Claim 1 is illustrative of the claimed invention, and it reads as
follows:
1. An averaging measurement circuit comprising:
a register adapted to successively store a series of data
words having a plurality of bits, said register adapted to
provide, for each of said data words, a first output signal
comprising all of the plurality of bits of the data word and a
second output signal comprising a number of the higher order bits
of the data word;
a subtracter adapted to subtract each second output signal
of said register from a corresponding data sample and output a
corresponding subtraction result; and
an adder to add each first output signal of the register to
a corresponding subtraction result and store the result in said
register.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Ito 4,829,460 May 09, 1989
Ono et al. (Ono) 5,448,508 Sep. 05, 1995
Claims 1, 4, 6, 9, 11, 17, and 20 stand rejected under
35 U.S.C. § 102(b) as being anticipated by Ono.
Claims 5, 10, 16, and 21 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over Ono.
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