Appeal No. 2004-0507
Application No. 09/476,862
stored in a buffer memory reaches a predetermined amount which is
equivalent to the writing capacity of the data processing
circuit. According to Appellant (specification, pages 3 and 4)
the suspension of operation, effected by either interrupting the
power supply or halting the supply of an operating clock, results
in a reduction of power consumption. Further provided is a
synchronization feature which enables new data to be recorded
successive to the recording region where the last data was
recorded before the suspension of operation.
Claim 3 is illustrative of the invention and reads as
follows:
3. A recording data processing circuit for processing
received data sent at a slower data transmission speed than
a data processing speed at which to write recording data
onto a non-erasable, write-once disk, comprising:
a buffer memory for temporarily storing the received
data;
a data processing circuit for preparing the recording
data to record onto the disk, based on the received data
read from the buffer memory;
a system control circuit for controlling writing and
reading of the received data with respect to the buffer
memory, and the operation of the data processing circuit,
and
a writing circuit for writing the recorded data
supplied from the data processing circuit, onto the disk,
2
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