Appeal No. 2004-0507
Application No. 09/476,862
wherein
the system control circuit suspends operation of the
data processing circuit until an amount of received data
equivalent to a predetermined writing capacity has been
stored in the buffer memory, and releases suspension of the
operation of the data processing circuit when an amount of
received data equivalent to the predetermined writing
capacity has been stored in the buffer memory, said data
processing circuit for recording data being placed in a
suspended state by interrupting the power supply or by
halting the supply of an operation clock,
wherein
the system control circuit stores an address
successive to an address of received data last recorded onto
the disk, as a recording start address on the disk, and
controls the writing circuit so as to write the recording
data supplied from the data processing circuit onto the disk
at the recording start address,
and wherein
the system control circuit synchronizes the recording
data to be newly recorded onto the disk, supplied from the
data processing circuit to the writing circuit, with
recording data recorded on the disk, said data processing
circuit being operated in synchronism with a reproduction
clock obtained by reproducing the data already recorded on
the disk.
The Examiner relies on the following prior art:
Landry et al. (Landry) 5,434,997 Jul. 18, 1995
Shinada 5,436,875 Jul. 25, 1995
Claims 3-12, all of the appealed claims, stand finally
rejected under 35 U.S.C. § 103(a) as being unpatentable over
Shinada in view of Landry.
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