Appeal No. 2004-0538
Application No. 09/976,495
memory, see page 5 of appellants’ specification.
Claim 1 is representative of the invention and reproduced below:
1. A multi-processor computer system comprising:
a plurality of processors;
a plurality of caches, each of said plurality of caches operatively connected to
one of said plurality of processors;
a first system control unit operatively associated with one of said plurality of
processors and operatively connected to one of said plurality of caches,
said system control unit having a cache flushing engine operatively
connected to said one of said plurality of caches;
a second system control unit operatively associated with said first system control
unit and operatively connected to said cache flushing engine;
a memory operatively connected to said second system control unit; and
said first system control unit responsive to an update of said one of said plurality
of caches operatively connected therewith to flush said update to said
second system control unit and assure said update is entered into said
memory.
References
The references relied upon by the examiner are:
Appellants admitted prior art (AAPA) on pages 1-3 of the originally filed
specification.
James et al. (James) 5,961,623 Oct 5, 1999
(filed Aug. 29, 1996)
Hagersten 5,892,970 April 6, 1999
(filed July 1, 1996)
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