Appeal No. 2004-0538
Application No. 09/976,495
ensure that when a node writes a new value to the memory block, all other nodes see this
latest value.” We do not find that the coherence protocol functions to “flush” the cache as
is claimed, as this section of the AAPA is discussing the case where a node is writing
data to it’s own memory block and not the memory block of another node. Thus, we do
not find that the AAPA teaches a first system control unit, with a cache flushing engine,
where the first control unit is responsive to an update of one of said plurality of caches
operatively connected therewith to flush said update to a second system control unit and
assure said update is entered into said memory, as is claimed. Accordingly, we will not
sustain the examiner’s rejection of claim 1.
We next turn to the rejection of claims 2 through 6 under 35 U.S.C. § 103.
Claims 2 through 6 are dependent upon claim 1, and as such necessarily include the
same limitations as claim 1. The examiner has not asserted that either Hagersten or
James teaches of suggests cache flushing, but rather the examiner relies upon Hagersten
and James to teach the limitations directed to buffers. See pages 3 and 5 of the
Examiner’ Answer. We do not find that James teaches flushing. As addressed supra, we
do find that Hagersten addresses the function of flushing. However, we do not find that
Hagersten teaches the interrelationship between the first and second control units and the
flushing engine as is claimed. Accordingly, we will not sustain the rejection of claims 2
through 6.
Other issues
Though, the issues is not before us, we note that dependent claim 4 introduces the
limitation “a temporary buffer connected through said second system control unit to said
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