Appeal No. 2004-0593
Application No. 09/606,688
nonintrusive observability of very sensitive internal nodes in
mixed-signal integrated circuits (Id., page 5, lines 4-5).
Further details of the claimed invention are found in the claims
reproduced above.
The Rejection of Claims 1-4, 7-10, 13-16, 25, 27, 31, 35,
and 39_Under 35 U.S.C. § 102(b)
The examiner has found that Rempfer discloses a multi-stage
circuit wherein each stage has electrically parallel branches of a
first transistor connected in series with a second transistor, and
a third transistor connected in series with a fourth transistor.
The second and fourth transistors are of an inverse type to that
of the first and third transistors (NMOS and PMOS transistors,
respectively). (Examiner’s Answer, page 3, line 19 - page 4, line
3).
The examiner has also found that the transistors are matched,
as in an integrated circuit the transistors are considered to be
matched unless otherwise stated. (Id., page 4, lines 4-6).
The examiner has finally found that Rempfer describes a gate
interconnection electrically connecting gates of a first and
second transistor to one another and an intermediate electrical
connection directly connecting all of the gates of the third and
fourth transistors, an intermediate point between the first and
4
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