Appeal No. 2004-0619
Application No. 10/061,140
1. A method of manufacturing a metal-oxide-semiconductor
transistor structure, comprising:
forming a plurality of dielectric isolation regions in a
semiconductor substrate;
forming a first dielectric layer outwardly from the
semiconductor substrate;
forming a polysilicon layer outwardly from the first
dielectric layer;
etching a portion of the polysilicon layer to form a gate;
forming at least one notch in a first side of the gate;
etching a portion of the first dielectric layer to expose the
semiconductor substrate;
forming an n+ source region in the semiconductor substrate
adjacent the first side of the gate;
forming an n+ drain region in the semiconductor substrate
adjacent a second side of the gate; and
forming at least one p+ substrate contact region proximate the
notch and adjacent the n+ source region.
The references set forth below are relied upon by the Examiner
in the § 102 and § 103 rejections before us:
Shirai 5,422,505 June 6, 1995
Burr 6,110,783 Aug. 29, 2000
Claims 1-3 and 14-16 stand rejected under 35 U.S.C. § 102(e)
as being anticipated by Burr; claims 4 and 17 stand rejected under
35 U.S.C. § 103(a) as being unpatentable over Burr; and claims 5
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