Appeal No. 2004-0856 Page 2
Application No. 09/676,704
memories 16a-16n. Each FIFO is implemented as an independent physical memory,
which the appellants consider "inefficient." (Id. at 2.)
In contrast, Figure 2 of the specification shows that the appellants' storage
element 111 comprises one or more virtual, multiqueue FIFO memories 103a-103n. A
circuit 110 detects a fastest one of a plurality of clocks (write_clk and read_clk) and
operates the storage element in a single clock domain (FAST Clock Domain)
corresponding to the faster clock. (Appeal Br. at 3-4.)
A further understanding of the invention can be achieved by reading the following
claim (indentations added):
1. A circuit configured to provide a storage element comprising one or
more virtual multiqueue FIFOs, wherein said circuit is configured to
(i) detect a fastest one of a plurality of clocks and
(ii) operate said storage element in a single clock domain
corresponding to said fastest one of said plurality of clocks.
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