Appeal No. 2004-0856 Page 6
Application No. 09/676,704
aforementioned, the examiner admits that Leong "does not disclose that his device
detects a fastest one of a plurality of clocks and operates in a clock domain of that
fastest clock." (Examiner's Answer at 4.) He alleges, however, "[w]hen Leong's device
was modified to work with devices having different clocks, then the device would
necessarily operate in the clock domain of the faster clock, since it would be able to
handle interfacing at the higher speed." (Id. at 7 (emphasis added).)
The examiner offers no evidence, however, to support his allegation. To the
contrary, evidence of record belies the examiner's assertion. "For example, FIG. 6 of
the Appellants' specification provides an example of a storage element capable of
operating in the clock domains of both an input device and an output device." (Reply
Br. at 3.) To wit, their specification explains that "[i]mplementing the dual port
memory 102' may eliminate a need for [a] [single] clock domain FAST_CLOCK_
DOMAIN. . . ." (Spec. at 19.)
Furthermore, Smith discloses that when "the transmission and receiving clocks at
a multiplexer point are not synchronized, a method to compensate for this lack of
synchronization is to provide a first-in, first-out (FIFO) buffer in which data is written into
the buffer using the transmission clock frequency and read from the buffer at the
receiving clock frequency." Col. 1, ll. 41-47. We are persuaded by the appellants'
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