Appeal No. 2004-1020
Application No. 09/486,908
If appellant is correct, then Pawlowski does not anticipate
the instant claimed invention because while the combination of
the main memory and the I/O module can provide an arbitrary
amount of data greater than one addressable cache line (admitted
by appellant at page 8 of the principal brief), this would still
require two accesses to the main memory. If the examiner is
correct, the rejection will be sustained because appellant argues
no other claim limitation.
We have reviewed the evidence of record and find ourselves
in agreement with the examiner.
There is nothing apparent in the instant claims which would
preclude the combination of Pawlowski’s main memory 14 and I/O
module as forming the claimed “data storage device.”
As further explained by the examiner, at page 7 of the
answer, Pawlowski’s peripheral 28 issues a data request to the
main memory/I/O Module combination. See column 2, lines 30-35,
of Pawlowski, where it states that the peripheral may request
less than a cache line of data in one transaction or it may
request greater than a multiple number of cache lines of data in
a transaction. Accordingly, appellant’s contention that
Pawlowski does not permit the access of the data storage device
in amounts other than the entire cache line would appear to be
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