Appeal No. 2004-1020
Application No. 09/486,908
inaccurate, as the background section of the reference clearly
indicates otherwise.
As explained in column 7, lines 15-30, of Pawlowski, while
the first cache line of data is being retrieved, the I/O
controller may cause the prefetch of consecutive cache lines of
data. Thus, while the main memory is retrieving the first cache
line of data, the combination of the main memory and the I/O
module results in the access of a “data storage device” in
amounts other than the entire cache line.
Moreover, we agree with the examiner’s reasoned analysis, at
pages 7-8 of the answer, wherein the examiner explained that the
amount of data that can be stored between two neighboring
starting addresses, e.g., starting addresses A & B, would be a
single cache line. A request resulting in the output of both the
initial cache line (cache line 1) and a prefetch line (cache line
2) would therefore output two cache lines. Thus, the amount of
data that can be stored between two neighboring start addresses,
viz., one cache line, would be smaller than the amount of data
output in response to the request, viz., two cache lines.
Appellant’s response is merely to argue that the examiner’s
interpretation of the combination of the I/O module and the main
memory comprising a “data storage device” is “inconsistent with
-7–
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