Appeal No. 2004-2144
Application No. 09/483,712
portions of the die, the dielectric element, the conductive
traces, the bond members and the carrier bonds (id.). The
examiner recognizes that Farnworth discloses all of the claimed
elements except the discrete conductive bond connecting the
conductive trace to the bond pad (id.). Therefore the examiner
applies Lee to show a similar chip-size package1 in which a
conductive trace is spaced from a bond pad, with a discrete
conductive bond in the form of a wire connecting the conductive
trace to a bond pad formed on the surface of a semiconductor chip
(id.).2 From these findings, the examiner concludes that it
would have been obvious to one of ordinary skill in the art at
the time the invention was made to employ the discrete conductive
1
1In the event of further or continuing prosecution of this
application, the examiner and appellants should consider whether
Lee alone discloses structures meeting the claimed limitations
(i.e., see Figures 9-11).
2
2The examiner states that the use of discrete electrical
bonds (lead or bond wires) was “notoriously well known” in the
art, as evidenced by appellants’ Figure 1 which is listed as
“Prior Art” (Answer, page 5). We also note that Figure 1 of Lee
is labeled as “PRIOR ART” and contains bond wires 80 connecting
bonding pad 74 to lead 76. It is axiomatic that admitted prior
art in an applicant’s specification may be used in determining
the patentability of a claimed invention (In re Nomiya, 509 F.2d
566, 570-71, 184 USPQ 607, 611-12 (CCPA 1975); and that
consideration of the prior art cited by the examiner may include
consideration of the admitted prior art found in an applicant’s
specification (In re Davis, 305 F.2d 501, 503, 134 USPQ 256, 258
(CCPA 1962); cf., In re Hedges, 783 F.2d 1038, 1039-40, 228 USPQ
685, 686 (Fed. Cir. 1986)).
4
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