Appeal No. 2004-2120 2
Application No. 09/987,566
a differential stage including a first insulated gate transistor and a second insulated
gate transistor,
said first insulated gate transistor receiving a power supply voltage as the first
voltage at a gate thereof and having a first conduction node, and a second conduction
node for outputting a difference signal, and
said second insulated gate transistor receiving a reference voltage as the second
voltage at a gate thereof and having a first conduction node connected to said first
conduction node of said first insulated gate transistor, said second insulated gate transistor
having a current supply ability different from a current supply ability of said first insulated
gate transistor under a condition of the same gate voltage, and said difference signal
corresponding to a difference between the first and second voltages, said reference
voltage determining a voltage level of an internal voltage generated from said power
supply voltage;
operation current supply circuitry for supplying an operation current to the first and
second insulated gate transistors, said operation current supply circuitry comprising a
current mirror coupled to the first and second insulated gate transistors for supplying
current to the first and second insulated gate transistors; and
a buffer circuit for buffering said difference signal for generating a binary level
detection signal indicating whether said first voltage is higher than said second voltage.
The reference relied on by the examiner is:
Bion et al. (Bion) 5,862,091 Jan. 19, 1999
(filed July 22, 1997)
Claims 19 and 20 stand rejected under 35 U.S.C. § 102(e) as being anticipated by
Bion.
Reference is made to the briefs (paper numbers 14 and 17) and the answer (paper
number 15) for the respective positions of the appellant and the examiner.
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