Ex Parte Young - Page 4



          Appeal No. 2004-2288                                                        
          Application No. 10/084,723                                                  

               Claims 1 through 3, 6, 8 through 11 stand rejected under               
          35 U.S.C. § 102(e) as anticipated by the disclosure of Nishizawa.           
          Claims 4 and 5 stand rejected under 35 U.S.C. § 103(a) as                   
          unpatentable over the disclosure of Nishizawa.  Claims 7 and                
          12 stand rejected under 35 U.S.C. § 103(a) as unpatentable over             
          the combined disclosures of Nishizawa and Shanks.                           
               We have carefully reviewed the claims, specification and               
          applied prior art, including all of the arguments and evidence              
          advanced by both the examiner and appellant in support of their             
          respective positions.  This review has led us to conclude that              
          the examiner’s aforementioned rejections are not well founded.              
          Accordingly, we will not sustain the examiner’s aforementioned              
          rejections for essentially those reasons set forth in the Brief             
          and the Reply Brief.  We add the following primarily for emphasis           
          and completeness.                                                           
               The examiner takes the position that Nishizawa teaches                 
          (Answer, pages 3-4):                                                        
               3.   Referring to claim 1, a flexible matrix array device              
               comprising: a thin film matrix circuit carried on the                  
               surface of a flexible substrate, (Figure 3b #3), which                 
               matrix circuit, (Figure 1), includes semiconductor devices,            
               (Figure 3b # 1a, 2a, 3a, & 4a[,] Col. 2[,] Lines 24-32),               
               arranged in a regular array and occupying respective first             
               areas, (Figure 3b examiner’s label #11), of the substrate,             
               (Figure 3b #3), and pixel electrodes, (Figure 1 #2),                   
               correspondingly coupled to each of the semiconductor                   
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