Appeal No. 2005-0287 Page 15
Application No. 09/216,214
device size can be minimized.4 See, e.g., the abstract, column
1, lines 50-60, column 2, lines 3-8 and column 6, line 44 through
column 7, line 24 of Watabe. That disclosure of Watabe is
consistent with the examiner’s stated rationale for combining
the applied references, as referred to above. That rationale for
the examiner’s rejection has not been specifically refuted by
appellant in the briefs before us in this appeal.5
4 Appellant appears to be concerned with the same problem.
As set forth at the paragraph bridging pages 2 and 3 of
appellant’s specification:
One of the long-standing problems in small field
effect transistors is hot carrier effects. When a
conventional MOS transistor structure is scaled down to
one micron or less, the potential energy of an electron
changes dramatically when it hits the N+ drain
boundaries. This sudden change in potential energy in a
short distance creates a high electric field. This is
undesirable because it causes the electrons to behave
differently within the semiconductor lattice. Electrons
which have been activated by high electric fields are
referred to as ‘hot electrons’, and can, for example,
penetrate into or through the gate dielectric.
Electrons which penetrate into, but not through, the
gate dielectric can cause the gate dielectrics to
become charged up over time. Thus, the behavior of the
transistor will gradually shift in the field, until the
transistor may fail in service. This is extremely
undesirable.
5 We note that arguments not made in the briefs are not
generally considered by the Board. See 37 CFR 1.192(a), as in
effect at the time the briefs were filed. That regulation has
recently been replaced. See 37 CFR 41.37(c)(vii).
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