Appeal No. 2005-0328
Application No. 09/723,655
Claim 9 is representative of the invention.
9. A process of manufacture of a MOSgated device comprising:
forming a gate oxide layer atop a silicon surface of one conductivity
type;
forming a layer of polysilicon atop said gate oxide layer; etching said
polysilicon layer and said underlying gate oxide layer into a plurality of
stripes of oxide and polysilicon spaced 1 to 4 microns and overlying said
silicon surface; implanting and diffusing a plurality of spaced first base
diffusion stripes of the other conductivity type into said silicon surface,
using said stripes of oxide and polysilicon as a mask; implanting and
diffusing a plurality of source diffusions into said first base diffusion
stripes, using said stripes of oxide and polysilicon as a mask, and leaving
invertible channel regions along the outer edges of said first base diffusion
stripes; implanting and diffusing second base diffusion stripes into said
silicon surface using said stripes of oxide and polysilicon as a mask, to a
depth below that of said source diffusions and extending to between the
opposite edges of adjacent pairs of said polysilicon stripes; wherein said
stripes of oxide and polysilicon do not include sidewall spacers during
implanting and diffusing of said first base diffusion stripes, said source
diffusions, and said second base diffusions.
References
The references relied upon by the examiner are as follows:
Davies 5,155,052 Oct. 13, 1992
Ajit et al. (Ajit) 5,474,946 Dec. 12, 1995
Rejection at Issue
Claims 9 through 14, 21 and 22 are rejected under 35 U.S.C. § 103 as
being unpatentable over Davies and Ajit as set forth on pages 5 through 7 of the
answer. Throughout the opinion we make reference to the briefs and the answer
for the respective details thereof.
2
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007