Appeal No. 2005-0499
Application No. 09/812,733
BACKGROUND
The invention relates to a processor including a large register file that utilizes a
dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of
the dirty bit storage. The dirty bit logic determines whether a register or a group of
registers in the register file has been written since the process was loaded or the
context was last restored. Representative claim 34 is reproduced below.
34. A context switch controller in a processor comprising:
a data storage unit divided into a plurality of storage groups;
a dirty bit storage coupled to the data storage and including one or more
storage bits corresponding to one or more respective storage groups in the data
storage unit; and
a dirty bit logic coupled to the dirty bit storage and configured to receive a
destination address of one or more instructions executing on the processor.
The examiner relies on the following reference:
Emer et al. (Emer) US 6,470,443 B1 Oct. 22, 2002
(effective filing date Dec. 31, 1996)
We refer to the Final Rejection (Paper No. 9) and the Examiner’s Answer (Paper
No. 20) for a statement of the examiner’s position and to the Brief (Paper No. 18) and
the Reply Brief (Paper No. 21)1 for appellants’ position.
Claims 1-28 have been canceled.
1 Although the examiner indicated that the Reply Brief was not entered (see Paper No. 22), the
examiner did not have authority to refuse entry of a timely filed reply brief. See 37 CFR § 1.193(b)(1)
(2004) (“The primary examiner must either acknowledge receipt and entry of the reply brief or withdraw the
final rejection and reopen prosecution to respond to the reply brief.”). However, the error was harmless,
because there were no substantive arguments in the Reply Brief requiring response.
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