Appeal No. 2005-0518 Page 2
Application No. 09/313,424
INTRODUCTION
The only remaining rejection is a rejection maintained under 35 U.S.C. § 103(a).1 As
evidence of obviousness, the Examiner relies upon the following two prior art references:
Hsu 5,468,657 Nov. 21, 1995
Sato et al. 6,121,117 Sep. 19, 2000
(filed July 20, 1998)
The specific rejection is as follows: Claims 16-21 and 23-25 stand rejected under 35
U.S.C. § 103(a) as being unpatentable over Hsu in view of Sato. (Answer, pp. 3-6).
Claim 16, the only independent claim, is illustrative of the invention on appeal:
16. A method of fabricating a semiconductor configuration, which comprises the
following steps:
fabricating a semiconductor structure having a base layer, an insulation layer, a
monocrystalline silicon layer, and an interface between the insulation layer and the
monocrystalline silicon layer;
placing a passivating substance X into the monocrystalline silicon layer, during or after
the fabrication of the semiconductor structure; and
heat-treating the semiconductor structure with the passivating substance X for causing
the passivating substance X in the monocrystalline silicon layer to diffuse both to the interface
and to a surface of the monocrystalline silicon layer opposite to the interface.
For the reasons presented in the Brief, particularly the reasons presented on pages 14 and
15, we reverse. We add the following primarily for emphasis.
1A rejection of claim 18 under 35 U.S.C. § 112, ¶ 2 has been withdrawn by the Examiner (Advisory Action
mailed November 18, 2003).
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