Ex Parte Amador et al - Page 1



               The opinion in support of the decision being entered                   
               today was not written for publication in a law journal                 
               and is not binding precedent of the Board.                             

                      UNITED STATES PATENT AND TRADEMARK OFFICE                       
                                                                                     
                         BEFORE THE BOARD OF PATENT APPEALS                           
                                  AND INTERFERENCES                                   
                                                                                     
                    Ex parte GONZALO AMADOR and ROGER J. STIERMAN                     
                                                                                     
                                Appeal No. 2005-0767                                  
                             Application No. 09/817,694                               
                                                                                     
                                      ON BRIEF                                        
                                                                                     
          Before KIMLIN, DELMENDO and PAWLIKOWSKI, Administrative Patent              
          Judges.                                                                     
          KIMLIN, Administrative Patent Judge.                                        

                                 DECISION ON APPEAL                                   
               This is an appeal from the final rejection of claims 1-5,              
          12, 16 and 17.  Claims 13-15 and 18-21 have been withdrawn from             
          consideration.  Claim 1 is illustrative:                                    
               1.  A method for controlled electroless plating of uniform             
          metal layers onto exposed metallizations in integrated circuits             
          positioned on the active surface of semiconductor wafers,                   
          comprising the steps of:                                                    
               maintaining a plurality of said wafers approximately                   
          parallel to each other at predetermined distances by supporting             
          an edge of each said wafers between a plurality of support means;           

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