Appeal No. 2005-0888
Application No. 10/039,663
1. An integrated circuit chip mounted on a
leadframe, said leadframe having a plurality of segments,
comprising:
a network of power distribution lines deposited on
the surface of said chip over active components of said
circuit;
said lines connected vertically to said components
by metal-filled vias, and also to said segments by
conductors; and
the majority of said lines patterned as straight
lines between said vias and said conductors,
respectively, thereby minimizing the distance for power
delivery between a selected segment and one or more
corresponding active components, to which said power is
to be delivered.
THE REFERENCES
Tani 5,468,993 Nov. 21, 1995
Yamasaki et al. 5,973,554 Oct. 26, 1999
(Yamasaki)
Stanley Wolf and Richard N. Tauber (Wolf), Silicon Processing for
the VLSI Era - Volume 1: Process Technology 857-58 (Lattice Press,
2nd ed. 2000).
THE REJECTIONS
The claims stand rejected as follows: claim 1 under 35 U.S.C.
§ 102(b) as being anticipated by Yamasaki; claims 2 and 3 under 35
U.S.C. § 103 as being obvious over Yamasaki; claims 4, 5, 7, 8, 11,
15, 20, 21 and 23 under 35 U.S.C. § 103 as being obvious over
Yamasaki in view of Tani; claim 9 under 35 U.S.C. § 103 as being
obvious over Yamasaki in view of Tani and the admitted prior art;
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