Appeal No. 2005-0973
Application No. 09/740,669
1. An apparatus for scheduling a Direct Memory Access (DMA)
device having multiple channels, comprising:
a shift structure having a plurality of entries
corresponding to the multiple channels to be scheduled, wherein
each entry in said shift structure includes a plurality of
fields, and wherein each entry includes a weight that is
determined based on said plurality of fields; and
a comparison-logic circuit configured to sort said entries
based on their respective weights.
10. A method of scheduling multiple channels on a Direct
Memory Access (DMA) device, comprising:
writing a plurality of entries in a shift structure, wherein
each entry is associated with a channel on the DMA, and wherein
each entry includes a plurality of fields;
assigning weights to said entries based on said plurality of
fields;
sorting said entries based on said weights, wherein an entry
having the highest weight is sorted to the head of said shift
structure; and
reading said entry from the head of said shift structure to
service the channel associated with said entry.
The examiner relies on the following references:
Lee et al. (Lee) 5,504,919 Apr. 2, 1996
Bass et al. (Bass) 6,052,375 Apr. 18, 2000
Claims 5-8, and 14-18 stand rejected under 35 U.S.C. § 112,
first paragraph, as relying on a non-enabling disclosure.
Claim 9 stands rejected under 35 U.S.C. § 101 as being
inoperative and lacking utility.
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