Appeal No. 2005-1220
Application No. 09/270,606 Page 2
adding a slurry modifier to the slurry, wherein
the slurry modifier combined with CMP slurry polishes
low structure areas at a substantially zero rate and
polishes high structure areas at a rate approximating a
blanket polishing rate without the use of a dummy
structure; and
polishing the silicon dioxide layer without
polishing any dummy structure using the modifier-
containing slurry, whereby the low structure areas are
polished at a substantially zero rate and the high
structure areas are polished at a rate approximating
the blanket polishing rate without using any dummy
structure.
13. A method of fabricating an integrated circuit
using CMP comprising:
providing a substrate with an overlying silicon
dioxide layer, and without any dummy structure such
that the silicon dioxide layer forms low structure
areas and high structure areas, without any dummy
structure;
forming a CMP slurry having a high structure
polishing rate lower than a blanket polishing rate;
adding a slurry modifier to the slurry to produce
a modified slurry that polishes high structure at a
rate approximating the blanket polishing rate; and
polishing the high structure areas of silicon
dioxide, whereby the high structure area are polished
at a rate approximating the blanket polishing rate
without using any dummy structure.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Kodera et al. (Kodera) 5,445,996 Aug. 29, 1995
Grover et al. (Grover) 5,759,917 Jun. 02, 1998
Burke et al. (Burke) 5,934,978 Aug. 10, 1999
Claims 1-20 stand rejected under 35 U.S.C. § 103(a) as being
unpatentable over Kodera in view of Grover and Burke.
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