Appeal No. 2005-1869
Application No. 09/902,051
The examiner relies on the following reference:
Patti et al. (Patti) 6,359,743 Mar. 19, 2002
(filed Nov. 20, 1998)
Claims 1-10 stand rejected under 35 U.S.C. §102 (e) as
anticipated by Patti.
Reference is made to the brief and answer for the respective
positions of appellant and the examiner.
OPINION
The examiner asserts that Patti discloses an offset
correction circuit to correct DC offset (identifying Figure 3,
element 102, and stating that “a thermal asperity causes a DC
offset,” pointing to Figure 2A) in accordance with a data rate
(identifying column 6, lines 51-56, for this teaching),
comprising a detection circuit to detect a thermal asperity
signal (identifying Figure 3, element 106, for this teaching),
and a filter circuit to respond to the thermal asperity signal in
accordance with the data rate (identifying Figure 3, element 112,
and column 6, line 55, for such a teaching).
For the further limitations of instant claim 6, the examiner
identifies Figures 1, 12, and 14 of Patti as teaching a disk
2
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