Appeal No. 2005-1800
Application No. 09/204,479
1. A processor comprising:
a register file; and
a functional unit, coupled to the register file, that
executes an instruction that operates upon plural registers of
said register file, including at least one register explicitly
identified by an explicitly defined register specifier and at
least one other register implicitly identified by the explicitly-
defined register specifier.
The prior art references of record relied upon by the
examiner in rejecting the appealed claims are:
Raghunathan et al. (Raghunathan) 4,300,195 Nov. 10, 1981
Baxter 5,826,096 Oct. 20, 1998
Andrew S. Tanenbaum, Structured Computer Organization, Prentice-
Hall, Inc. (1976) pp. 75-87. (Tanenbaum)
Claims 1, 3 through 6, 8 through 17, 19 through 21, 23, and
24 stand rejected under 35 U.S.C. § 103 as being unpatentable
over Baxter in view of Tanenbaum.
Claims 7 stands rejected under 35 U.S.C. § 103 as being
unpatentable over Baxter in view of Tanenbaum and Raghunathan.
Reference is made to the Examiner's Answer (Paper No. 33,
mailed March 8, 2004) for the examiner's complete reasoning in
support of the rejections, and to appellants' Brief (Paper No.
2
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