Appeal No. 2006-0380
Application 10/445,783
THE INVENTION
The appellants claim a CMOS circuit having feedback circuits
that prevent pull-up and pull-down transistors from being on
simultaneously. Claim 1 is illustrative:
1. A CMOS circuit including a pull-up transistor and a
pull-down transistor, comprising:
(a) a first feedback circuit having an input
directly coupled to a gate of the pull-up transistor and an
output coupled to a gate of the pull-down transistor;
(b) a second feedback circuit having an input
directly coupled to the gate of the pull-down transistor and an
output coupled to the gate of the pull-up transistor;
(c) the first feedback circuit producing a first
delayed signal on the gate of the pull-down transistor to turn on
the pull-down transistor a first predetermined amount of time
after the pull-up transistor is turned completely off so as to
prevent any shoot-through current from flowing through the pull-
up transistor and the pull-down transistor; and
(d) the second feedback circuit producing a second
delayed signal on the gate of the pull-up transistor to turn on
the pull-up transistor a second predetermined amount of time
after the pull-down transistor is turned completely off so as to
prevent any shoot-through current from flowing through the pull-
up transistor and the pull-down transistor.
THE REFERENCES
McClure 5,349,243 Sep. 20, 1994
Nolan 6,653,878 Nov. 25, 2003
(filed Sep. 24, 2001)
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