Appeal No. 2006-0380
Application 10/445,783
THE REJECTIONS
The claims stand rejected as follows: claims 1, 3 and 15-17
under 35 U.S.C. § 102(b) as being anticipated by McClure, and
claims 1-3 and 15-17 under 35 U.S.C. § 102(e) as being
anticipated by Nolan.
OPINION
We affirm the aforementioned rejections.
Rejection over McClure
McClure discloses a latch controlled output driver (90)
comprising 1) latches 94 and 96, each having a PMOS transistor
(P1 and P2, respectively), and 2) an output driver (92)
comprising NMOS pull-up (T1) and pull-down (T2) transistors
(col. 2, line 48 - col. 3, line 3). Latches 94 and 96 are
connected, respectively, to the gates of transistors T1 and T2
(abstract; figure 2). Transistors P1 and P2 ensure that
transistors T1 and T2 are not on at the same time (col. 1,
line 68 - col. 2, line 4; col. 3, lines 36-41).
The appellants argue that in McClure “[t]here is no mention
of a delay signal” (brief, page 10).
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