Appeal No. 2006-1458
Application No. 10/040,395
gates are electrically coupled together as are the N+ regions
enabling the voltage across the silicon gates and the N+ regions
to control the capacitance of the varactor.
Claim 32 is illustrative of the invention and reads as
follows:
32. A method of making a varactor comprising:
forming a plurality of alternating P- wells and N+ regions
in a silicon layer of an SOI structure, wherein the P- wells form
N+/P- junctions with the N+ regions, and wherein each of the P-
wells and the N+ regions extends completely through the silicon
layer to an insulation layer of the SOI structure;
forming a plurality of gate oxides, wherein each of the gate
oxides is formed above a corresponding one of the P- wells;
forming a plurality of silicon gates, wherein each of the
silicon gates is formed above a corresponding one of the gate
oxides;
electrically coupling each of the silicon gates together;
and,
electrically coupling each of the N+ regions together.
The Examiner’s Answer cites the following prior art:
Chiang et al. (Chiang) 5,038,184 Aug. 06, 1991
Tsang1 5,563,438 Oct. 08, 1996
Litwin et al. (Litwin) 6,100,770 Aug. 08, 2000
1 The Tsang reference is cited by the Examiner as providing evidence but is
not part of the stated ground of rejection.
2
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