Appeal No. 2006-1595
Application No. 09/798,484
hardware description language (HDL). The invention also automatically specifies
an appropriate source code function library configuration depending on whether a
stand-alone source code simulation or mixed-language simulation is performed.
Representative claim 1 is reproduced as follows:
1. An apparatus for automatically specifying the configuration of a mixed-
language model to be simulated in a simulator, the mixed-language model
comprising at least one model to be written in a source code language and at
least one model written in a hardware description language (HDL), the apparatus
comprising:
a first logic identifying hierarchy paths within the source code model;
a second logic identifying hierarchy paths within the source code model
that correspond to hierarchy paths in the HDL model;
a third logic identifying connections within the source code model to be
enabled or disabled; and
a fourth logic identifying portions of the source code model that are to be
modeled by the source code model and portions of the source code model that
are to be modeled by the HDL model.
The examiner relies on the following references:
Shinde et al. (Shinde) 5,493,507 Feb. 20, 1996
Parson 6,053,947 Apr. 25, 2000
Hellestrand et al. 6,263,302 Jul. 17, 2001
(Hellestrand) (filed Jan. 26, 2000)
Burgoon, David A., A Mixed-Language Simulator for Concurrent Engineering,
IEEE, Mar. 1998 (“Burgoon”).
Martinolle, Froncoise, A Procedural Language Interface for VHDL and its Typical
Applications, IEEE, Mar. 1998 (“Martinolle”).
2
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