Appeal No. 2006-1595
Application No. 09/798,484
and nodes are instantiated in order to build the C
model hierarchy [specification, page 18].
Regarding the limitation calling for identifying hierarchy paths in the source
code model that correspond to hierarchy paths in the HDL model, the
specification states:
After the C model has been built, the Verilog
“initialization”…blocks are executed, as indicated by
block 23…Each GET and PUT call knows where it
was called from in the Verilog model hierarchy.
These calls use their respective hierarchy paths in the
Verilog model to find the corresponding hierarchy
paths in the C model [specification, page 19].
The limitations calling for (1) identifying connections within the source
code model that are enabled or disabled, and (2) identifying portions of the
source code model to be modeled by the source code and HDL models
respectively are described as follows:
From [a] tagging process, the C model can determine
which ports are active in the C model and which are
not. Ports in the C model that are inactive correspond
to portions of the C model that are to be simulated
with the Verilog model. Ports in the C model that are
active correspond to portions of the mixed-language
model that will be simulated with the C model portions
and the resulting signals will be processed and
interfaced to the Verilog model portions by the CVI
modules 10 [id.].
Furthermore, regarding claims 7, 21, and 23, we find ample support for the
claimed subject matter in the specification on at least Page 3, lines 1-8, Page 17,
line 36 – Page 18, line 9 (describing loading C code within a shared library for
either stand-alone source code or mixed-language simulations and specifying the
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