Appeal No. 2006-2051
Application No. 10/396,955
BACKGROUND
Claim 1 is representative of the claimed invention and is
reproduced as follows:
1. An underfill for an integrated circuit package
comprising:
a base material; and
a filler material constitutes a selected percentage by
weight of the underfill to provide an optimum balance
between interfacial die stress of a low-k dielectric laver
of an integrated circuit die and solder bump strain for
reliability of the integrated circuit package.
REJECTIONS AT ISSUE
A. Claims 1 through 7 and 17 through 21 stand rejected under 35
U.S.C. § 103 as being unpatentable over the combination of
Admitted Prior Art (APA), Chan (US Patent Application No.
2004/0086719) and Jayaraman (US Patent No. 6,724,091). We refer
herein to the Examiner’s Answer (mailed on March 8, 2006).
REASONS FOR REMAND
The Examiner’s statement of the rejection of claims 1
through 7 and 17 through 21, at page 4 of the Examiner’s Answer,
alleges that the claims are unpatentable over the combination of
2
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