Appeal No. 2006-2920 Page 5
Application No. 10/813,501
together, we will consider independent claim 1 as the representative claim
for this rejection. See 37 C.F.R. § 41.37(c)(1)(vii)(2004).
Appellants argue that Asada fails to disclose the limitation of
“configuring a first circuit of the self-gated transistor to disable the transistor
substantially upon a positive current flow through the transistor,” as claimed
[brief, page 4; reply brief, page 5; see also claim 1, emphasis added]. With
respect to the portions of the reference relied on by the examiner, appellants
specifically argue that Asada’s circuit of fig. 5 (and fig. 4) does not have a
mode of operation that disables transistors 10 and 841 responsive to a
positive current flow through transistor 10 [brief, page ]. Appellants argue
that Asada’s circuit of fig. 5 (and fig. 4) disables transistors 10 and 841
responsive to the voltage Vs (and the current through resistor 801) being
less negative than reference voltage Vr [brief, page ].
The examiner disagrees [answer, page 7]. Specifically, the examiner
notes that Asada discloses the reference voltage Vr is negative and nearly
ground potential [id.; see Asada, col. 6, lines 21 and 22]. The examiner
asserts that “nearly ground potential” is a potential equal to or very close to
ground, e.g. less than 1/10 millivolt [answer, page 7]. The examiner asserts
that the output of Asada’s comparator 840 would not change state to turn
off transistor 841 immediately after the voltage potential at its negative
input terminal increases from a potential below Vr to a potential above Vr
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