Appeal No. 2006-3034 Page 8
Application No. 09/855,115
In particular, we note that in one embodiment Dieterich’s rate control
module 630 (fig. 6) uses side information to determine whether the buffer
fullness level is at a state that will allow the use of a finer quantization scale
[col. 6, lines 40-45]. Clearly, this portion of the reference fails to meet the
language of the independent claims that requires reading (or outputting)
stored data from the buffer at a bit rate determined at least partially by the
fullness of the buffer. As pointed out by the examiner, fig. 6 shows an
arrow to the right of buffer 690 that represents the compressed video signal
as read from the rear the FIFO buffer. However, we find no disclosure in
Dieterich that specifically describes how the bit rate of this output video
signal is controlled [see e.g., col. 6, lines 18-23]. As pointed out by
appellants, Dieterich specifically discloses that rate control module 630
serves to monitor and adjust the bit rate of the data stream entering FIFO
buffer 690 [col. 6, lines 24-26]. Therefore, we find that Dieterich does not
fairly disclose reading (i.e., outputting) the stored data out of the buffer at a
bit rate determined at least partially by the fullness of the buffer.
Because Dieterich fails to disclose every element and limitation of the
claimed invention, we agree with appellants that the examiner has failed to
meet his/her burden of presenting a prima facie case of anticipation.
Accordingly, we will not sustain the examiner’s rejection of independent
claims 1 and 6. Because we have reversed the examiner’s rejection of each
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