Representative claim 12 is reproduced as follows:
12. A transistor comprising:
a drain terminal comprising a doped polysilicon material disposed within a
first shallow cavity formed in an isolation oxide region;
a source terminal comprising a polysilicon material disposed within
second hallow cavity formed in the isolation oxide region;
a channel formed in a silicon material and arranged between each of the
first shallow cavity and the second shallow cavity, wherein the channel comprises
a respective doped region coupled to each of the drain terminal and the source
terminal; and
a gate disposed over the channel and comprising one or more conductive
layers disposed over a gate oxide layer.
The examiner relies on the following references:
Tsuchiaki 6,271,566 Aug. 7, 2001
Michejda et al. (Michejda) 2002/0190344 Dec. 19, 2002
The following rejections are on appeal before us:
1. Claim 12 stands rejected under 35 U.S.C. § 102(e) as being anticipated by
Michejda.
2. Claims 13-25 stand rejected under 35 U.S.C. § 103(a) as being unpatentable
over Michejda in view of Tsuchiaki.
Rather than repeat the arguments of appellants or the examiner, we make
reference to the briefs and the answer for the respective details thereof.
OPINION
We have carefully considered the subject matter on appeal, the rejections
advanced by the examiner and the evidence of anticipation and obviousness relied
upon by the examiner as support for the rejections. We have, likewise, reviewed and
taken into consideration, in reaching our decision, the appellants' arguments set forth in
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