Appeal No. 2006-3138
Application No. 09/683,351
BACKGROUND
Appellants’ invention relates to a method for handling 32-bit results for an out-of-
order processor with a 64-bit architecture. An understanding of the invention can be
derived from a reading of exemplary claim 1, which is reproduced below.
1. A method for operating a processor having an architecture of a
larger bit-length with a program comprising instructions compiled to
produce instruction results of at least one smaller bit-length, characterized
by the steps of:
detecting when in program order a first instruction is to be
dispatched which does not have a target register address as one of its
sources, wherein the first instruction is one of the instructions compiled
to produce instruction results of at least one smaller bit-length;
adding an extract instruction into an instruction stream before the
first instruction, the extract instruction comprising the following steps of:
a. dispatching the extract instruction together with the following
first instruction from an instruction queue into a Reservation Station;
b. issuing the extract instruction to an Instructional Execution
Unit (IEU) as soon as all source operand data is available and an IEU is
available according to respective issue scheme;
c. executing the extract instruction by an available IEU;
d. setting an indication that the result of said extract instruction
needs to be written into a result field of the first instruction following the
extract instruction, and;
e. writing the extract instruction result into the result field of
said first instruction, and into all fields of operands being dependent of
said first instruction.
PRIOR ART
The prior art references of record relied upon by the Examiner in rejecting the
appealed claims are:
Mahurin et al. (Mahurin) 6,493,819 Dec. 10, 2002
Isaman et al. (Isaman) 6,449,710 Sep. 10, 2002
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