Appeal 2006-2499
Application 10/268,735
(1) Lin discloses an improved TaN copper barrier for a copper
damascene process with improved adhesion to low k dielectric
layers where the integrated circuit comprises a barrier layer (19)
deposited on a substrate, an adhesion layer (20) deposited on the
barrier layer (19), a seed layer (24) deposited on the adhesion layer
(20), and electroplating a conductive layer (26) on the seed layer
(24) to form a highly reflective surface (Answer 3; Lin, Fig. 1C;
Abstract; col. 3, ll. 1-7; col. 3, ll. 24-44; col. 5, ll. 49-67; and col.
9, ll. 11-12 and 19-20);
(2) Lin exemplifies a stoichiometric barrier layer (19) between about
230 and 285 Angstroms thick, while teaching that the standard
TaN barrier is a conventional single composition TaN layer of
comparable thickness to the Lo/HB composite barrier (col. 5, ll.
32-34, and col. 6, ll. 12-14);
(3) Singhvi discloses an effective barrier layer for improved via fill in
high aspect ratio sub-micron apertures, desiring a minimal
thickness of the metallization stack and avoidance of an increased
barrier layer thickness (Abstract; col. 2, ll. 25-33; and col. 5, ll. 19-
22 and 46-50);
(4) Singhvi discloses a substrate layer, a dielectric layer deposited on
the substrate layer, a barrier/wetting layer, which may be TaN,
deposited on the dielectric layer, with subsequent deposition of a
seed layer and a metal (Al or Cu) layer on the barrier/wetting
layer, and teaches the most preferred thickness of 100 to 400
4
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Last modified: September 9, 2013