Appeal 2007-0399
Application 09/961,024
2. Baker teaches an interface device compatible with computer
industry standards for controlling the transfer of data packets
between devices in a computer environment. (Col. 5, l. 24).
Reading Baker’s PCI-Serial Bus Interface #20 (Figure 1) as the
claimed interface device, including from Figure 2 DMA Logic
72 and LLC Logic 90, we read the elements of claim 1 on
Baker as expressed by the Examiner on page 3 of the Answer.
3. The operation of this device is explained by Baker in column
19, lines 7 to 16.
While moving data from GRF 80 [General Receive
FIFO] to the PCI interface logic 70, DMA engine
74 waits for GRF 80 to have sufficient data before
requesting the PCI bus master to perform a
transfer. This transfer threshold is reached
whenever one of two conditions is met. DMA
engine 74 will request a transfer of the PCI master
whenever the number of bits in the receive FIFO
reaches a "high water mark". This high water mark
is equal to the greater of the cache line size register
or the lower bound field of the DMA global
register.
4. It is noted that this operation holds, or stops, the transfer of data
from the receive FIFO until the number of bits in the receive
FIFO reaches a certain threshold, after which a signal
commences the transfer from the FIFO.
5. Earnest teaches a multi-channel data interface controller in
which single FIFO transmit and receive circuits communicate
through a plurality of logical channels. (Earnest, Col. 2). To
6
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 Next
Last modified: September 9, 2013