Appeal 2007-0439
Application 10/630260
the ‘906 patent is “simply inapplicable” does not indicate the
error in applying the claimed limitations as Examiner indicated.
4. With respect to claims 2 to 5, we note in Figure 6a that bus 675
carries the output of controller 510, using all data bits (indicated
as D[0:15]. We note in the same figure that the signals along
bus segment 680 contain the low order data bits (D[0:7]) and
those long bus segment 684 contain the high order data bits
(D[8:15]). Thus it is not an error to read the unified bus logic,
using all the data bits, on the controller 510.
5. With respect to claim 6 to 8, we can comprehend the
Examiner’s argument about the possibility of the item 670
being conceptually embodied in multiple chips. However,
inherency requires a stronger showing, namely that the inherent
characteristic is necessarily as indicated in the rejection. See
the Continental Can Co. case below. Items 670 and 672 are
described in ‘906, column 6, line 60 ff as “a first flash memory
chip 670 designated FLASH0 and a second flash memory chip
672 designated FLASH1.” We do not find support in ‘906, nor
in the Wikipedia definition of flash memory, of the claimed
three components being necessarily provided in separate
integrated circuit chips.
6. With respect to claims 9 and 10, we note in Figure 6a of ‘906
connections between the flash memory chips 670 and 672.
Portions of the information from each of the memory chips is
channeled to host 504 (Figure 6b) through these connections
connecting the two chips. Examiner has read each of these two
recited memory chips as the two claimed intermediate
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